SPI0 external RAM mode control register
| SPI_MEM_SCLK_MODE | SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. |
| SPI_MEM_SWB_MODE | Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit. |
| SPI_MEM_SDIN_DUAL | For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. |
| SPI_MEM_SDOUT_DUAL | For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. |
| SPI_MEM_SADDR_DUAL | For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. |
| SPI_MEM_SDIN_QUAD | For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. |
| SPI_MEM_SDOUT_QUAD | For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. |
| SPI_MEM_SADDR_QUAD | For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. |
| SPI_MEM_SCMD_QUAD | For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. |
| SPI_MEM_SDIN_OCT | For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. |
| SPI_MEM_SDOUT_OCT | For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. |
| SPI_MEM_SADDR_OCT | For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. |
| SPI_MEM_SCMD_OCT | For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. |
| SPI_MEM_SDUMMY_RIN | In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. |
| SPI_MEM_SDUMMY_WOUT | In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. |
| SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT | In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller. |
| SPI_SMEM_WDUMMY_ALWAYS_OUT | In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller. |
| SPI_SMEM_DQS_IE_ALWAYS_ON | When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others. |
| SPI_SMEM_DATA_IE_ALWAYS_ON | When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others. |